A Framework for Side-Channel Resistant Hardware/Software Codesign Using Quantum Crypto-Module (QCM) Supported by Quantum Entropy Chip (QEC) (N31c)
With the advent of the Internet of Things (IoTs), all kinds of modern electrical devices such as smart phones, medical devices, network sensors as well as traditional computing platforms are connected to the Internet, and IoT security has become a significant concern. To prevent cybersecurity attacks, security mechanisms for user authentication and data integrity using cryptographic protocols must be embedded in the devices. Typically, the primary driving factor in the IoT applications aims to deliver the highest value IoT product at the lowest cost. Unfortunately, implementing cryptographic security protocols in any environment is resource intensive in MCU, RAM and ROM which IoT devices often find difficult to support. Hardware/software codesign can increase the throughput of the cryptographic module by lightening a load of a MCU with hardware accelerators. However, general cryptographic implementations are vulnerable to side-channel attacks, such as differential power analysis and correlation power analysis attacks.
In addition, random bit generators play a pivotal role in generating security primitives, e.g., encryption keys, nonces, initial vectors, and random masking for side-channel countermeasures. For forward and backward unpredictability as well as an increase of entropy, the National Institute of Standards and Technology (NIST) approved cryptographic algorithm is used for deterministic random bit generators (DRBGs) such as HASH-DRBG, HMAC-DRBG, and CTRDRBG. However, general implementations of DRBGs are susceptible to side-channel attacks as well.
We propose a framework for side-channel resistant hardware/software codesign using quantum crypt-module (QCM) supported by EYL’s proprietary quantum entropy chip (QEC). QEC is a non-deterministic random bit generator that extracts randomness from time intervals between radioactive isotope decay events. The framework supports a hardware/software development board including two FPGAs, an ARM Cortex-M4 MCU and a quantum entropy chip (QEC), side-channel resistant primitives such as quantum random numbers and random frequency clocks, and a software tool to evaluate the throughput, power consumption and side-channel resistance of the hardware/software implementation. In addition, a cryptographic library in hardware/software including AES, RSA, ECC, SHA-2/3, and RNGs is provided for developing efficient cryptographic applications. Quantum random numbers and Random frequency clocks generated by Quantum Entropy Chip (QEC) can be utilized for side-channel countermeasures such as hiding and masking techniques. The framework will provide cryptographic designers with an efficient and side-channel resistant design methodology and a preliminary implementation.