May 11-13, 2022 | Washington, DC

Open Cryptographic Instruction Set Design: The RISC-V Scalar Cryptography ISE (S32b)

03 Sep 2021
14:00-14:30

Open Cryptographic Instruction Set Design: The RISC-V Scalar Cryptography ISE (S32b)

The RISC-V Instruction Set is a popular free and open alternative to historically closed CPU Instruction Set Architectures (ISAs) like ARM and x86. RISC-V’s collaborative ecosystem, and lack barriers to entry in terms of licensing costs, have made it a popular choice for many recent embedded and application class CPU cores from a wide range of companies; including those focused on security generally, and cryptographic modules specifically. RISC-V features a very small core ISA, which is extended with various application or domain specific extensions. One such extension currently in development and nearing completion is the Scalar Cryptography ISE. It focuses on making accelerated cryptographic processing available to even the smallest embedded core designs. It adds a small number of general purpose instructions and lightweight special purpose instructions for very popular algorithms like AES and SHA2. RISC-V is the first ISA to add make dedicated cryptographic acceleration available to embedded class cores. It also adds guarantees for instruction-level data-independent execution latency. This talk gives an overview of the RISC-V Scalar Cryptography ISE from the editor of the draft specification. We start with an overview of the RISC-V ecosystem, and describe its public development process involving industry and academia. We then describe the improved functionality which RISC-V generally, and the Scalar Cryptography ISE specifically provide with respect to cryptographic module design; including the performance improvement of key algorithms and approximate hardware cost overheads. We finish with expected standardization timelines, and pointers for how to start exploring and developing with the ISE.